The present invention relates generally to integrated circuits, and more particularly to an output circuit having multiple operating modes for use in memory devices and other integrated circuits.
Memory devices are integral to a computer system and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enable operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and the data/control lines within the memory devices. Faster operating speed can be obtained by reducing the charge and discharge times of parasitic capacitance on internal data lines and by improving the data-clocking scheme within the memory devices.
Conventionally, a memory access to retrieve a data bit is performed by: (1) activating a row control line (e.g., a row select line or a word line) for the data bit; (2) waiting for the charge that is stored in a memory cell corresponding to the data bit to generate a voltage on a sense line; (3) sensing the charged voltage on the sense line to determine the value of the data bit; (4) activating a column select line; (5) providing the detected bit value to a data line, and (6) buffering and providing the data bit to an input/output (I/O) pin of the memory device. Conventionally, these steps are performed in sequential order for each accessed data bit. These steps define the access time of the memory device (i.e., to read a data bit), which in turn determines the data transfer rate.
The data bit retrieved from the memory cell is typically provided to an output circuit, which often includes a data synchronization circuit and an output driver circuit. The data synchronization circuit is conventionally implemented with either a latch or a register. Each of these implementations is advantageous for some situations (i.e., certain timing scenarios and operating conditions), and may not be advantageous for other situations. For example, the timing of the data and clock signal provided to the data synchronization circuit can vary with power supply and temperature. For a particular implementation (i.e., latch or register output circuit), variations in the timing relationship between the data and clock can degrade timing margins and can even impact product yields. To account for timing variations, the period of the clock signal can be "lengthened", which however corresponds to slower operating speed.
As can be seen, an output circuit capable of operating under different timing relationships and operating conditions is highly desirable.